1. Field of the Invention
The present invention relates to a computer program product, system, and method for locking a cache line for write operations on a bus.
2. Description of the Related Art
A central processing unit (CPU) may write data to a cache for the purpose of writing over a bus to another device in a system. To optimize transferring data over a bus, such as a Peripheral Component Interconnect (PCI) bus, the CPU may gather write data in a cache to burst over the bus in a single transaction, as opposed to multiple individual operations. Existing embedded controller systems use a method of cache line flushes to peripheral busses and hardware to improve overall system performance. This method includes clearing a processor cache line using a Data Cache Block Set to Zero (DCBZ) instruction, filling the cache line with data to be transmitted, and then flushing the cache line using a Data Cache Block Flush (DCBF) instruction. This process avoids any reads from the peripheral hardware, such as that which would occur on the write of a first single word of a cache line to bring the block of data into the cache. It also allows for the write of a cache line of data, typically 32 bytes, to occur as a burst on the peripheral buss rather than being performed as 8 single word writes.
If an interrupt is taken during the building of the cache line, then there is a risk that the cache line could be selected by a cache line replacement algorithm to be cast out and replaced by a new line of data. When the CPU returns from the interrupt, if the cache line was cast out, then the CPU will have to rebuild the cache line by reading the data from an address in memory. The system/hardware may not support a read of data from these addresses (only writes are allowed), so an error condition is created. Existing implementations prevent the data from being cast out from the cache line by disabling interrupts, completing this cache line fill and flush process, and then re-enabling interrupts.
There is a need in the art for improved techniques for performing writes to cache lines and managing the cache lines in cache.